1. Field of the Invention
This invention relates to a memory device which employs a plurality of shift registers.
While this invention is applicable to all sorts of memories employing shift registers, it will be specifically described in the case of magnetic bubbles in the present specification.
2. Description of the Prior Art
The principle of magnetic bubbles was discovered by Andrew H. Bobeck of Bell Telephone Laboratories, Inc. and his associates, and is being extensively investigated for memory devices. The details are described in "Magnetic Bubbles" by A. H. Bobeck et al., Scientific American, Vol. 224, June 1971, pp. 78-91. With the progress of magnetic bubble technology, memory devices exploiting it have become increasingly large in capacity. One of problems in the fabrication of a large-capacity magnetic bubble chip is posed by a defect in the magnetic substance which holds the magnetic bubbles and a defect in the permalloy pattern which is made thereon. As the capacity of a chip becomes larger and the density becomes higher, the probability that the whole chip becomes defective and will have to be discarded on account of only one defect becomes higher. That is, the yield is lowered, and the desire to reduce the bit cost by large capacity and high density is nullified.
Let it be supposed that even when a chip including 256 loops has two defective loops, it is usable. Assuming that the probability at which the chip has no defect is 10%, that the probability at which it has one defective loop is 26% and that the probability at which it has two defects is 32%, then the yield is the sum of the probabilities, i.e., about 70%. In other words, the yield increases to 7 times greater, and the bit cost is reduced to 1/7.
In a construction in which a memory portion for information is made up of a single shift register only, if a defect exists in any place on the loop, there will be no expedient for avoiding the defective loop because all the bubbles pass through the defect. In contrast, in a major-minor type organization, the memory portion is divided into independent minor loops, and hence, a control for avoiding the use of loops including defects is possible.
To this end, a defective loop memory circuit is provided outside the memory chip. Prior to the operations of reading, writing and erasure, the addresses of the defective loops are detected from the defective loop memory circuit, whereby the control sequence of a rearrangement circuit for a pulse train is determined. Subsequently, information is read out from the memory chip, and the pulse train having been disarranged on account of the defective loops not to be used is restored to the correct pulse train by the pulse train rearrangement circuit. The writing is similar, and is executed in such a way that the pulse train rearrangement circuit rearranges the pulse train of correct order into the disordered pulse train in accordance with the defective loops not to be used.
Unless the defect loop address memory is non-volatile, the defective loop address information will be lost and will become unrecoverable upon disconnection of the power supply. Unless the address memory is low in bit cost, its cost will not be negligible. Since the magnetic bubble memory is non-volatile, it can be utilized for the defective loop address memory. For example, U.S. Pat. No. 3,792,450 discloses a defective loop address memory which is formed on the same chip as that of the storage loops.
In the device disclosed in the above-referenced U.S. patent, a "1" is written into respective minor loops, After the information goes round each minor loop shifted to a major loop through a transfer gate. In that case, the information cannot pass through loops including defects. The information shifted to the major loop is subsequently stored into a defective loop address memory. The defective loop address memory information is read out by the use of a detector separate from the one provided for storage loops before information from the storage loops are read out. That is, the defective loop address memory consists of minor loops in the number of bits equal to the number of the storage loops. One bit is allotted to each loop, and whether the loop is a defective one or an operative one is represented by the designation "1" or "0" ,respectively.
The prior-art device accordingly has the advantage that it can be used even in the case where most of the minor loops are defective loops. It is disadvantageous, however, in that the number of bits increases with the memory capacity, the access time becoming undesirably long.
By way of example, assume that up to four defective loops are permitted in a chip of the major-minor type organization being of 1 M bits per chip and having 512 minor loops. Chips which have five or more defective loops are of a slight number. Even when they are made defective chips, the overall yield scarcely changes.
In such case, the access time increases by 1024-bit time with the bit expression of the respective loops as stated above. The access time is effectively doubled in comparison with the access time in the case where the defective loop address memory is not provided. Moreover, according to the prior-art device, each chip has an individual detector for reading out defective loop addresses, so that peripheral circuits become considerably bulky.